Staff Digital Design Verification

The Advanced Cores Group is seeking a motivated individual for an opportunity to contribute to key design verification tasks for Analog Devices' next generation IPs, integrated circuits, design IPs, modules and systems.

Requirements

• Define test-plans, tests and verification methodology for block/chip-level verification
• Work with the design team in generating test-plans and closure of code and functional coverage
• Utilize Directed and Constrained random verification techniques along with System Verilog assertions
• Be proficient in architecting and developing UVM testbenches at block and chip level
• Be proficient in writing testcases to execute on the testplan using System Verilog and C (for firmware cosimulations)
• Verify complex designs and sub-systems using leading edge verification methodologies
• Be proficient in debugging RTL and Gate Level Simulation (GLS), waiving Timing Violations approved by the designers
• Demonstrate the ability to automate various verification tasks using languages such as Python
• Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
• Be familiar with Digital Signal Processing concepts, and tools such as MATLAB or Octave
• Be able to document work through good English writing and reading skills for widening the knowledge base
• Be familiar with Formal Verification techniques and approaches
• Be able to effectively communicate with Mixed-Signal Design Verification and the Firmware teams
• Have effective interpersonal, teamwork, and communication skills enabling the candidate to contribute and influence decisions on methodologies/strategies to be adopted for verification
• Technically mentor and guide junior verification engineers on SoC Verification