Principal Engineer, Design Verification

Analog Devices is seeking a Principal Engineer, Design Verification to contribute to the verification of complex designs and sub-systems using leading edge verification methodologies. The successful candidate will have experience in ASIC design verification, IP and SoC level verification, and a strong understanding of verification-plan generation, coverage analysis, and formal verification techniques.

Requirements

• Verification of complex designs and sub-systems using leading edge verification methodologies
• Contribution to and influence on decisions on methodologies/strategies to be adopted for design verification
• Development of testbench architectures and testing using UVM or Formal based verification approaches
• Definition of verification-plans, functional coverage, tests and verification methodology for block/chip-level verification
• Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
• Continuous interaction with analog co-sim and firmware team
• Mentorship and guidance of junior verification engineers on SoC Verification
• Support of post-silicon verification activities of the products working with design, product evaluation and applications engineering team
• Leadership of verification efforts at IP or SoC level, effort estimation, project scheduling and tracking, task assignment, reporting to management or customer

Benefits

• Competitive salary
• Benefits package
• Opportunities for career growth and development
• Collaborative and dynamic work environment
• Equal opportunities employer