Principal Engineer, Design Verification

Analog Devices is seeking a Principal Engineer, Design Verification to contribute to the verification of complex designs and sub-systems using leading edge verification methodologies. The role will involve developing testbench architectures, defining verification-plans, and debugging gate level simulation. The ideal candidate will have a strong background in verification-plan generation, coverage analysis, and formal verification techniques with System Verilog.

Requirements

• Bachelor's or master’s degree in Engineering (Electronic Engineering) or equivalent
• 10-15 years in ASIC design verification
• Strong interpersonal, teamwork and communication skills
• Customer facing experience as verification lead
• Experience in both IP and SoC level verification
• Strong demonstrable knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion based and formal verification techniques with System Verilog
• Expert in developing unit and SoC level test benches using UVM
• Excellent debugging and analytical skills
• Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.