ASIC RTL Engineer

The ASIC RTL Engineer is responsible for all aspects of SoC subsystem design, including IP design, integration, testing, and support. This role requires expertise in various design disciplines, utilizing Verilog/System Verilog and scripting languages. The ideal candidate will also have strong knowledge of AMBA protocols and understanding of timing concepts.

Requirements

• Expertise in SoC subsystem/IP design
• Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
• In-depth knowledge on RTL quality checks (Lint, CDC)
• Knowledge of synthesis and low power
• Knowledge of one or more of the interface protocols (e.g., PCIe, DDR, Ethernet, I2C, UART, SPI)
• Good understanding of timing concepts
• Knowledge of one or more of the interface protocols (e.g., AMBA)
• Good understanding of script languages (Make flow, Perl, shell, python)
• Understanding of processor architecture and/or ARM debug architecture is a plus