Silicon Labs is seeking a Lead RTL Design Engineer to develop, integrate, and verify digital RTL blocks within mixed-signal subsystems. The engineer will work closely with system architects, analog designers, and SoC teams to enable seamless integration of mixed-signal IPs into complex SoCs.
Requirements
- Develop synthesizable, high-quality RTL for mixed-signal IPs
- Collaborate with analog design engineers to define digital-analog interface specifications
- Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components
- Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses
- Collaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digital and analog boundaries
- Integrate mixed-signal IPs into SoC top-level RTL and resolve functional or timing issues during full-chip validation
- Contribute to continuous improvement of design methodologies, automation scripts, and reuse strategies for mixed-signal IP development
Benefits
- Equity Rewards (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Insurance plans with Outpatient cover
- National Pension Scheme (NPS)
- Flexible work policy
- Childcare support
