Staff Verification Design Engineer

Staff Verification Design Engineer is responsible for performing block and chip-level verification, running simulations, and developing tests to ensure tape-out quality.

Requirements

• 3+ years experience in semiconductor industry
• M.S. in EE/CS/CE or higher
• Hands-on experience with System Verilog as High-level Verification Language and UVM implementation
• Debugging digital simulation in both RTL and gate-level netlist
• Scripting experience in Python or Perl
• Clear understanding of ASIC design flow
• Solid analytical, synthesis and problem solving skills
• Independent, self-motivated, rigorous, team player and able to follow through
• Excellent verbal and written communication skills

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan
• Visa Sponsorship
• Four Day Work Week
• Generous Parental Leave
• Tuition Reimbursement
• Relocation Assistance