Staff Design Engineer - Integration

Design engineer will generally be responsible for the integration of different IPs to build the fullchip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign-off.

Requirements

• BS or MS in Electronics/Computer/Electrical Engineering
• At least 8 years of proven in-depth experience in Custom and Digital Design Implementation
• Expertise in Verilog and System Verilog is a must
• Experience in FPGA/CPLD design and integration is a plus
• Expertise on the following: Custom Design Flow, Semiconductor principles and transistor-level analysis, Industry standard tools for schematic and layout Entry (Cadence Virtuoso), Characterization, performance, and power simulations (spice is preferred)
• Digital Design Flow, RTL coding and verification, Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus)
• DFT flow and ATPG generation
• Experience in IP and Fullchip functional verification is a plus
• Expertise in coding/scripting (Perl, TCL, Shell, Skill, Phyton)
• Experience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus

Benefits

• Comprehensive compensation and benefits program
• Attract, retain, motivate, reward and celebrate the highest caliber employees