Senior Digital Verification Engineer (DAC/ADC DSP Correction)

Ciena is committed to a people-first approach with a flexible work environment that empowers individual growth, well-being, and belonging. As a Senior Digital Verification Engineer, you will be part of a team responsible for implementing innovative verification strategies for the Wavelogic family of products.

Requirements

• Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
• Thoroughly validate one or more architectural functional blocks using a combination of simulation, formal, and coverage methods.
• Develop verification, functional coverage and formal verification test plans.
• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and/or C.
• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.
• Provide regular status updates on verification progress on a regular basis.

Benefits

• Comprehensive benefits package
• Medical, dental, and vision plans
• 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave
• Vacation time