At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We're looking for a Principal Design Engineer to join our team.
Requirements
- Complete DFT ownership of projects including test architecture definition, RTL changes, scan insertion, LEC checks, low power CLP checks, timing constraints, scan and ATPG, boundary scan, ACJTAG, IEEE 1500 implementation and verification, IEEE1687 (iJTAG) compliant ICL/PDL, and zero delay and timing simulations.
- Experience working on very high speed and low power designs.
- Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Benefits
- Generous Paid Time Off
- 401k Matching
- Retirement Plan
- Visa Sponsorship
- Four Day Work Week
- Generous Parental Leave
- Tuition Reimbursement
- Relocation Assistance