Lead Design Engineer

Cadence is hiring a Lead Design Engineer for SOC Design in Shanghai. The ideal candidate has hands-on experience with protocol like AMBA, PCIe, USB, MIPI or DDR/LPDDR and ARM/RISC-V Processor integration experience. Collaboration with verification teams, customer and internal engineering teams is required.

Requirements

• Bachelor's/Master's in Electrical/Computer Engineering or related field
• 3+ years experience in digital SOC design
• Expertise in SOC or IP design, SOC integration, RTL coding, synthesis and basic understanding of timing constraints
• Experience in front end design checks like LINT, CDC, RDC, UPF and constraint checks / validation
• Good Communication in English