Technical Lead Design Verification Engineer

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. We are looking for a Senior Design Verification Engineer with a flair for being a code breaker to contribute to the functional verification of complex ASICs.

Requirements

• Strong academic and technical background in electrical engineering
• ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
• Knowledge of industry-standard simulators, revision control systems, and regression systems
• Experience with full verification lifecycle based on System Verilog/UVM/C/C++
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random
• Experience with different ways to bug and coverage hunting

Benefits

• Competitive salary range (USD 147,000.00 – USD 195,000.00)
• Encouragement of diversity and inclusion