IP Logic Design Engineer - Advanced Technologies Group

As IP Logic Design Engineer, you will combine RTL implementation and Micro-Arch, collaborating with teams to deliver elite PHY designs, develop verification environment, and participate in next-generation PHY architecture.

Requirements

• B.Sc or M.Sc Electrical Engineering or Computer Engineering
• 4+ years of Logic Design experience
• Advanced knowledge of standard ASIC verification flows
• Excellent knowledge of System Verilog, Verilog
• Working knowledge of Extraction and STA methodology and tools
• Experience with either Perl/Tcl scripts
• Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers