SiPearl is building European high-performance low-power processors dedicated to supercomputing and AI. This new generation of processors will first target EuroHPC Joint Undertaking ecosystem, which is deploying world-class supercomputing infrastructures in Europe for solving strategic sovereign challenges in security, defense, generative AI, medical research, security, energy management and climate with a reduced environmental footprint. SiPearl is working in close collaboration with its 30 partners from the European Processor Initiative (EPI) consortium - leading names from the scientific community, supercomputing centres and industry - which are its stakeholders, future clients and end-users. SiPearl employs 200 people in France, Spain and Italy
Open Positions
[CDI] Linux Kernel Engineer
Strong expertise in Linux kernel development and low-level software, solid understanding of hardware / OS interactions, and experience with CI environments
[CDI] Senior FPGA prototyping engineer
Strong expertise in FPGA development and prototyping on complex platforms, solid knowledge of HDL languages, timing constraints and advanced design rules, ability to architect robust solutions, professional proficiency in English, strong communication skills and scientific rigor
[CDI] Senior system architect
Minimum 7 years of experience as a System Architect, proven experience in HPC environments, strong debugging skills and scientific rigor
[CDI] Technical Project Manager
10+ years of experience in technical program management, expertise in export compliance, and strong leadership skills
[CDI] Senior CAD flow engineer
Strong expertise in ASIC design flows, leadership and mentoring skills
[CDI] Benchmark Cloud & HPC engineer
Strong experience in benchmarking and performance analysis in Cloud and/or HPC environments, solid knowledge of programming languages and parallel computing models, and strong collaboration and communication skills
[CDI] Semi-conductor Program Manager
5-10 years of experience, engineering degree, ability to translate company vision into executable projects
[STAGE] - Interconnect design
Knowledge of complex digital system architectures, digital design flows, RTL, synthesis, placement/routing, autonomy, initiative spirit and taste for teamwork
[CDI] Senior IP subsystem SoC architect
Strong technical skills, leadership, and communication skills required
[CDI] Senior verification engineer
Minimum 7-10 years of experience in ASIC/SoC verification, team management, and leadership
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